---------------------------------------------------------------------------
--
-- SRAM
-- 32 bit wide 
-- 32 words	  
-- Dual port
-- output data is LATCHED by rising edge of RD
--
-- Paul Maddox
-- Http://www.FPGA.Wavesynth.com/
--
-- When useing Synplify change the Library (comment out UNISIM)
-- when useing Xilinx Webpack Use UNISIM (comment out virtex)
---------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------- 
-- Copyright (c) 2002, Paul Maddox
-- All rights reserved. 
-- 
-- Redistribution and use in source and binary forms, 
-- with or without modification, 
-- are permitted provided that the following conditions are met: 
-- 
--    * Redistributions of source code must retain the above copyright notice, 
--       this list of conditions and the following disclaimer. 
--    * Redistributions in binary form must reproduce the above copyright notice, 
--       this list of conditions and the following disclaimer in the 
--       documentation and/or other materials provided with the distribution. 
--    * Neither the name of Modulus electronics nor the names of its contributors 
--       may be used to endorse or promote products derived from this software 
--       without specific prior written permission. 
-- 
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
-- 
---------------------------------------------------------------------------------------------------------- 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;						-- for Webpack 
use UNISIM.Vcomponents.ALL;		-- library that holds RAM16X1D primative

--Library Virtex;						-- for Synplify
--use Virtex.Components.ALL;		-- library that holds RAM16X1D primative

package RAM32X32DL_pack is
	component RAM32X32DL							-- ports for 8 bit unit
	port (
			WE			:in std_logic:='0';
			Din			:in std_logic_vector (31 downto 0);
			WCLK		:in std_logic:='0';	
			RD			:in std_logic:='0';
			Addr		:in std_logic_vector (4 downto 0);	-- address
			Dout		:out std_logic_vector (31 downto 0)	-- read address data out
			);
 	end component;

  	component RAM16X1D							-- ports for 1 bit unit (primative)
	port (
			WE			:in std_logic;
			D			:in std_logic;
			WCLK		:in std_logic;
			A			:in std_logic_vector (3 downto 0);	-- Write address
			DPRA		:in std_logic_vector (3 downto 0);	-- Read address
			SPO			:out std_logic;						-- write address data out
			DPo			:out std_logic						-- read address data out
			);
	end component;
end RAM32X32DL_pack;

---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;
use UNISIM.Vcomponents.ALL;

--Library Virtex;						-- for Synplify
--use Virtex.Components.ALL;		-- library that holds RAM16X1D primative


entity RAM32X32DL is
	port (
			WE			:in std_logic:='0';
			Din			:in std_logic_vector (31 downto 0);
			WCLK		:in std_logic:='0';
			RD			:in std_logic:='0';
			Addr		:in std_logic_vector (4 downto 0);	-- address
			Dout		:out std_logic_vector (31 downto 0) -- read address data out
			);
end RAM32X32DL;

---------------------------------------------------------------------------

architecture structure of RAM32X32DL is

signal data0	:std_logic_vector(31 downto 0);
signal data1	:std_logic_vector(31 downto 0);
signal we_int0	:std_logic;
signal we_int1	:std_logic;

begin
ram0loopx:
	for i in 0 to 31 generate 
	ram0: RAM16X1D 
		port map (
				WE => WE_INT0,
				D => Din(i),
				WCLK => WCLK,
				A3 => Addr(3),
				A2 => Addr(2),
				A1 => Addr(1),
				A0 => Addr(0),
				DPRA3 => Addr(3),
				DPRA2 => Addr(2),
				DPRA1 => Addr(1),
				DPRA0 => Addr(0),	
				DPO => data0(i)
 				);
end generate;
ram1loopx:
	for i in 0 to 31 generate 
	ram1: RAM16X1D 
		port map (
				WE => WE_INT1,
				D => Din(i),
				WCLK => WCLK,
				A3 => Addr(3),
				A2 => Addr(2),
				A1 => Addr(1),
				A0 => Addr(0),
				DPRA3 => Addr(3),
				DPRA2 => Addr(2),
				DPRA1 => Addr(1),
				DPRA0 => Addr(0),	
				DPO => data1(i)
 				);
end generate;

process(RD)			-- read process
begin
	if RD'event and RD='1' then	--if we get a rising edge then latch data
		if addr(4)='1' then
			Dout <= data1;
		else
			Dout <= data0;
		end if;
	end if;
end process;

process(addr(4)) 	-- process for 5th bit of address
begin
	if addr(4)='1' then
		we_int0<='0';
		we_int1<='1';
	else
		we_int0<='1';
		we_int1<='0';
	end if ;
end process;

end architecture structure;