RAM32X32DL
32bit by 32word Dual port Ram with latched output
Submitted by Paul Maddox
This Module gives you 32 words, each 32bits wide. A single address bus is used for read/write operations.
Use:
To write data to the module Put the address onto Addr the data onto the Din bus and then put WE high, then pulse Wclk, it is rising edge triggered.
To read data from the module, simply put the address onto Addr.
then pulse RD, the output of that address will then be latched and the result will stay on Dout regardless of address and write signals
Source:
The VHDL source is here RAM32X32DL.VHD
It is free, but please leave the authors name and webpage link in the code
FPGA Synth